Field of the Invention
This disclosure relates generally to a memory-testing device and, more particularly, to an effective memory-testing method with an adjustable clock signal to optimize the timing slack of the memory-testing device.
Description of the Related Art
FIG. 1A is a block diagram of a system 10 including a memory 160 operated in a functional mode or a test mode. The system 10 includes a logic unit 110, testing circuitry 120, a register 142 and a memory 160. There are several timing paths for accessing the memory 160 including a first timing path TP1 from the original clock signal CK of the memory 160 to the output DO of the memory 160, a second timing path TP2 from the output DO of the memory 160 through the logic unit 110 to the register 142, and a third timing path TP3 from the output DO of the memory 160 to the testing circuitry 120. When the memory 160 is accessed or operated on the functional mode for normal operation, the corresponding timing paths of the functional mode are the first timing path TP1 and the second timing path TP2. When the memory 160 is accessed or operated on the test mode, the corresponding timing paths of the test mode are the first timing path TP1 and the third timing path TP3.
Specifically, the testability mainly depends on the timing margins of the second timing path TP2 and the third timing path TP3, especially when there is a delay or fault on the first timing path TP1. However, if the timing margin of the third timing path TP3 is larger than or looser than the second timing path TP2, the testing reliability and the accuracy of the testing circuitry 120 will deteriorate. For example, on the one hand, the testing result is normally successful when the memory 160 is in the test mode, but on the other hand, the practical performance or result fails when the memory 160 is in the functional mode. Therefore, a better memory-testing method is needed to decrease the gap of the timing margins between the second timing path TP2 and the third timing path TP3 for improving the reliability and accuracy of testing the memory.
Various kinds of testing devices or methods have been utilized to test the timing paths and the performance of the memory 160. For example, the Automatic Test Pattern Generation (ATPG) test has been widely used. When the memory 160 is accessed or operated during the at-speed testing of the ATPG, the critical access should be applied on the memory 160. Since the critical path is from the pre-charging of the bit line to the next access cycle, there could be some failures in the output DO of the memory 160 if the critical path is too tight to pre-charge the bit line to a pre-determined voltage level. In addition, the size of the test pattern of the ATPG is very large. Therefore, the testing procedure of ATPG is inefficient and also costs too much time and money, and another memory-testing method with high efficiency and low cost is needed.